Integrated circuit manufacturing processes involves a plurality of deposition steps, including the deposition of metal layers, dielectric layers, polysilicon layers, etc. These processes also involve the deposition of blanket layers and gap fillings. For example, the formation processes of Shallow Trench Isolation (STI) regions involve the filling of trenches in semiconductor substrates with dielectric materials.
It is difficult to maintain the within-wafer uniformity in the thickness of the deposited layers. The deposited layers often have different thicknesses in the regions close to the center axis of the wafers and the regions close to the edges of the wafers. Furthermore, the within-wafer uniformity is also affected by the configurations of production tools. The within-wafer uniformity has effect on subsequent process steps and manufacturing yield, and a low within-wafer uniformity may result in the loss in the manufacturing yield.